1. Field of the Invention
The present invention relates to an interface circuit, and more particularly to an interface circuit for performing a data transfer between first and second units which are asynchronous with each other., i.e., whose data rates are different or whose data rates are the same but phases are different.
2. Prior Art
In the field of the digital audio technique or data communication technique, it is sometimes necessary to perform the data transfer between the first and second units which are asynchronous with each other. In such asynchronous state, if the data transfer is performed regardless of the synchronization between the first and second units, data reading error must be occurred. Particularly, in some cases, the first clock pulse frequency of the first unit is extremely close to the second clock pulse frequency of the second unit, and the frequency difference between the first and second clock pulse frequencies is due to the frequency difference between the crystal vibrators thereof. In such cases, once the timing of write pulse for writing the data into the output register in the first unit becomes close to that of read pulse by which the second unit reads the data from the output register, there must be a possibility in that the data reading errors are continuously occured during several to several tens of periods. However, in the case where there is a sufficiently large phase difference between the write pulse of the first unit and the read pulse of the second unit, such errors can be avoided.
Conventional, in order to avoid the above data reading error, the following interface circuits are employed.
(1) Interface Circuit Using Phase-Locked Loop (PLL)
In FIG. 1, 1 designates a first register into which the output of first unit is to be written: and WP designates a write pulse by which the data is written into the first register 1. In addition, 2 designates a second register of the second unit into which the output of first register 1 is to be written. The output of this second register 2 is fed to the second unit. Further, 3 designates a PLL which generates a clock pulse in synchronism with a clock pulse CLK, and this generated clock pulse is fed to a timing generator 4. Based on this clock pulse from the PLL 3, the timing generator 4 generates a read pulse RP, which is then fed to the second register 4. FIG. 2 shows timing charts of this circuit as shown in FIG. 1.
This interface circuit can synchronize the read pulse RP with the write pulse. Therefore, the errors can be avoided. However, this interface circuit is disadvantageous in that its configuration for the clock system in the second unit must be complicated.
(2) Interface Circuit Using First-In/First-Out (FIFO) Register
This interface circuit uses the FIFO register as shown in FIG. 3. When the read/write ratio of this FIFO register is nearly at "1", there is no problem. However, when the write period is always shorter than the read period so that the write cycle is always faster than the read cycle, there must be a problem in which the data to be written overflows the capacity of the FIFO register.
(3) Interface Circuit Using Sampling Frequency Converter
This interface circuit uses the sampling frequency converter as shown in FIG. 4. Since the over-sampling process, low-pass filtering process, decimation process and the like are executed within this interface circuit, the error can be avoided. However, similar to the foregoing interface circuit using the PLL, it is disadvantageous in that the configuration of this interface circuit must be complicated.
As described heretofore, the conventional interface circuits are disadvantageous in that the configuration must be complicated and the production cost must be raised.